`timescale 1ns/1ps
module ProgramModeFlipFlop(PMI, PMO, PME, rst, clk);
  input [1:0] PMI;    //Program Mode in: the inputted mode
  input PME;          //Program Mode enable: the enable so that the mode can be programmed
  input rst;          //reset: resets the flip flop, defaults to 00 or access for all times for everyone; low enable
  input clk;          //clock: the clock for the whole system
  output [1:0] PMO;   //Program Mode out: the output(current) program mode
  
  wire [1:0] PMI;
  wire PME;
  wire rst;
  wire clk;
  reg [1:0] PMO;
  
  always @ (posedge clk or posedge rst)
  begin
    if(PME == 1'b1)
    begin
      PMO <= PMI;
    end
    else
    begin
      PMO <= PMO;
    end
  end
  
  always @ (negedge rst)
  begin
    PMO = 2'b00;
  end
endmodule

